Phase locked loops (PLLs) are typically used to generate a relatively stable, low jitter high frequency clock (e.g., at 3-4 GHz) from a low frequency reference, such as 100 MHz. A digital phase locked loop (DPLL) is a digital version of the PLL. The DPLL generally includes two sensitive components, a digitally controlled oscillator (DCO) and a time to digital converter (TDC). However, the performance of these components can shift to unknown values/characteristics.
The DCO generates an oscillatory output which frequency is controlled by a digital input. The gain of the DCO (KDCO) is defined as a frequency shift per code change and usually changes with transistor, inductor and capacitor target number.
The TDC takes two oscillatory inputs and converts the delay between them into a digital word. The TDC essentially quantizes the time difference or phase difference and converts that into a digital representation.
Shifts in the performance of the DCO and/or TDC can degrade communication performance by generating noise, distortions, and the like.